development:simd
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| development:simd [2025/10/30] – created hayati | development:simd [Unknown date] (current) – external edit (Unknown date) 127.0.0.1 | ||
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| + | ~~NOTRANS~~ | ||
| + | {{indexmenu_n> | ||
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| + | ====== SIMD ====== | ||
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| + | Modern processors have capabilities for SIMD (single instruction multiple data) like SSE or AVX instruction sets on x64 or NEON on ARM architecture. Now, in 2022, C/C++ compilers still have problems at automatic vectorization to generate these vector instructions. Assembler or compiler intrinsic functions can be used to enforce the usage .. | ||
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| + | ===== CPU architectures/ | ||
| + | |||
| + | * https:// | ||
| + | * https:// | ||
| + | * https:// | ||
| + | * https:// | ||
| + | * https:// | ||
| + | * does contain the L1/L2/L3 cache sizes | ||
| + | * Raspberry Pi 4 has Broadcom Chip BCM2711 | ||
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| + | |||
| + | ===== Libraries ===== | ||
| + | |||
| + | * https:// | ||
| + | * https:// | ||
| + | * https:// | ||
| + | * it's origin https:// | ||
| + | * SSE/AVX to Neon | ||
| + | * https:// | ||
| + | * https:// | ||
| + | * Neon for x86/SSE | ||
| + | * https:// | ||
| + | * SIMD Everywhere | ||
| + | * https:// | ||
| + | * https:// | ||
| + | * https:// | ||
| + | |||
